Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-N PLLs

We present an analytical frequency-domain phase noise model for fractional-N phase-locked loops (PLL). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump device noise, sigma-delta modulator (SDM) noise including its effect on the in-band phase noise. Thermal device noise of the charge pump and the turn-on time of the charge pump output current are found to be limiting the inband phase noise of state-of-the-art synthesizers. Device noise considerations for bipolar transistors and MOSFETs suggest the use of CMOS-only charge pumps (CP), even in BiCMOS technologies. We present a noise-optimized CMOS CP, specifically designed for a dual-loop PLL architecture using two CPs. This PLL architecture keeps the DC output voltage of the noiserelevant CP and the phase noise spectrum constant, regardless of temperature variations.